1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to decoding signals employed within such communication systems.
2. Description of Related Art
Data communication systems have been under continual development for many years. One such type of communication system that has been of significant interest lately is a communication system that employs iterative error correction codes. Of particular interest is a communication system that employs LDPC (Low Density Parity Check) code. Communications systems with iterative codes are often able to achieve lower BER (Bit Error Rate) than alternative codes for a given SNR (Signal to Noise Ratio).
A continual and primary directive in this area of development has been to try continually to lower the SNR required to achieve a given BER within a communication system. The ideal goal has been to try to reach Shannon's limit in a communication channel. Shannon's limit may be viewed as being the data rate to be used in a communication channel, having a particular SNR, that achieves error free transmission through the communication channel. In other words, the Shannon limit is the theoretical bound for channel capacity for a given modulation and code rate.
LDPC code has been shown to provide for excellent decoding performance that can approach the Shannon limit in some cases. For example, some LDPC decoders have been shown to come within 0.3 dB (decibels) from the theoretical Shannon limit. While this example was achieved using an irregular LDPC code of a length of one million, it nevertheless demonstrates the very promising application of LDPC codes within communication systems.
The use of LDPC coded signals continues to be explored within many newer application areas. Some examples of possible communication systems that may employ LDPC coded signals include communication systems employing 4 wire twisted pair cables for high speed Ethernet applications (e.g., 10 Gbps (Giga-bits per second) Ethernet operation according to the IEEE 802.3 an (10 GBASE-T) emerging standard) as well as communication systems operating within a wireless context (e.g., in the IEEE 802.11 context space including the IEEE 802.11 an emerging standard).
For any of these particular communication system application areas, near-capacity achieving error correction codes are very desirable. The latency constraints, which would be involved by using traditional concatenated codes, simply preclude their use in such applications in very high data rate communication system application areas.
When performing decoding processing of such LDPC signals within communication systems, a designer has quite a degree of freedom by which to implement the hardware to perform such decoding. By selecting a particular topological arrangement (in terms of hardware and processing resources) for implementing an LDPC code decoder. Depending on the particular design parameters desired to be optimized, a designer can select a particular decoder design to meet any one or more of various design objectives including meeting desired levels of area, time, and power that are required to decode such LDPC signals effectively and to an acceptable degree of performance for a given application. There seems continual to be a need in the art for more and better designs to allow a hardware device designer to select a particular arrangement to meet the particular needs of a particular application.